Chip-on-MEMS

New verified integration concept

VTI has developed and launched a new heterogeneous integration concept for combining MEMS devices and integrated circuits: chip-on-MEMS or CoM. The concept is based on a combination of VTI's wafer level encapsulated 3D MEMS technology, wafer level packaging (WLP) technology and chip-on wafer technology. All these elements of CoM have existed for a few years. Combining them in an innovative way solves the tough packaging problem of how to combine MEMS with circuits cost efficiently.

The technology consists of steps of applying redistribution and isolation layers on the MEMS wafer, dropping 300 micron solder balls, flip-chipping thinned ASICs and finally passivating the gap between the ASIC and MEMS by underfilling. The MEMS wafer is probed so that only known good sites will be populated. After completion of the process the wafer is diced and the final test performed when the dies are still on the dicing tape. Sensors are also calibrated while still on the tape.

The first MEMS device based on CoM, the 3-axis accelerometer CMA 3000 has a footprint of 4 mm2 and height of less than 1 mm. The second product, the 3-axis gyro CMR3000, has a footprint of 3x4 mm2 and a height of less than 1 mm.

A new direction for system integration

The flip-chipped CoM is the first step in VTI's heterogeneous integration roadmap. It is a radical step away from conventional packaging, which relies on integration on a carrier, either a pre-molded housing, a lead frame or a substrate. Eventually CoM will result in a smaller size and lower cost than any carrier-based packaging. All packaging will be just an extension of the processes of a wafer fab.

Although it is not the first ever demonstration of a wafer level combination of MEMS and circuits, CoM solves many issues that are present with the earlier approaches. In CoM the MEMS device and the ASIC are fully isolated in manufacturing: both can be 100% tested prior to combining. No area is wasted due to size mismatch or for the sealing between MEMS and the circuit.

The first implementation of CoM requires that the MEMS die is somewhat larger than the circuit and the I/O-count is limited. VTI is at the moment developing extensions of the CoM technology that will solve these limitations and further improve the cost efficiency of CoM.